Moving target signal processor

ABSTRACT

The moving target signal processor of one disclosed embodiment is adapted for use with a pulse compression type radar, and includes: a plurality of clutter canceller units having clutter rejection characteristics which are a function of the number of consecutive range sweeps, from any given antenna scan location, processed thereby; clutter detection circuits for providing alarm signals indicative of excessive clutter content in the uncompressed received signals and the canceller units&#39;&#39; uncompressed output signals, respectively; and logic control circuits responsive to the alarm signals, for controlling the number of transmissions at each scan location so that the processor&#39;&#39;s output signals have less than a predetermined clutter energy content.

ilnited States Patent 1191 Evans et al.

[ MOVING TARGET SIGNAL PROCESSOR [75] Inventors: Norol T. Evans, SanPedro; David D.

Etflnger, La Habra, both of Calif.

[73] Assignee: The Hughes Aircraft Company,

Culver City, Calif.

[ Filed: Nov. 1, 1971 [2]] Appl. No.: 194,424

1451 Aug. 28, 1973 Primary Examiner-Benjamin A. Borchelt AssistantExaminer-G. E. Montone A tiornev wf fl. Macallisterl Jr. and Lawrence \1Link, Jr. L

[5 7] ABSTRACT The moving target signal processor of one disclosedembodiment is adapted for use with a pulse compression type radar, andincludes: a plurality of clutter canceller units having clutterrejection characteristics which are a function of the number ofconsecutive [52] U.S. Cl. 343/7.7, 343/7.5 ran e SW88 8 from an ivenantenna scan location 51 Int. Cl. G015 9/42, GOls 9/10 missedlclutrgdetecfion circuits for 581 Field of Search 343/77, 7.5, 17.2 PC PP mg alarm signals indlcative of excesslve clutter content 5 6]References Cited 1n the uncompressed recelved s1gnals and thecancellerun1ts uncompressed output s1gnals, respectwely; and UNITED STATESPATENTS logic control circuits responsive to the alarm signals,3,341,847 9/1967 Friedet al. 343/75 for controlling the number oftransmissions at each 3,673,590 6/1972 F 343/7-7 scan location so thatthe processor's output signals 3,281,837 10/1966 Van Hnfte 343/75 haveless than a predetermined clutter energy content 27 Claims, DrawingFigures 36 from 87 3 From 74 B 1 PULSE 77 94 90 91 DUPPLEP- j 1PROCESSOR A/l.) RVD suuucrrou DIGITAL 0V1 DETECTOR 'ONVEiuu CIRCUITPULb'l- I cuMPiugbsou SWITCH a an acne from Fig. 1 PRF COUNT u zr zgiionDevice 6i of Fig. l I M'lI i-i'i'I DELAY PHASE A/D UNI'l DETECTORCONVERTER gggf l I 7 8 8T3 ICV s 1 20/ 1F signal K 'J from (.10 of Fig.l 73 RV CLUTTER DETECTOR DETECTION ic5 CIRCUIT J Alarm S1gnu|s 86 gm 90PRF LOGIC d from SEQUENCE CONTROL to Q 7 q pu commas :mcuzrm' @f 1 0tP19. 1

PRP Count TC 3 1 MOVING TARGET SIGNAL PROCESSOR BACKGROUND OF THEINVENTION This invention relates generally to MTI signal processors; andmore particularly to such processors which automatically select theappropriate level of MTI operation, and which may be used in pulsecompression type radar systems to reduce the clutter energy content inthe received radar signal prior to pulse compression.

Prior clutter recognition circuits in pulse compression radar systemshave generally been mechanized to detect clutter after the receivedradar signal has been compressed or decoded. Also these prior artsystems have not provided for automatic selection of the level of MTIoperation which maintains the clutter level in the output signal belowpreselected limits regardless of the type clutter environmentencountered, while minimizing the radar time on target.

Systems which attempt to recognize clutter signals after pulsecompression have several inherent shortcomings, such as requiring alarge dynamic range for both the pulse compression and MTI circuits. Alarge dynamic range is neededin these prior systems to accommodate thehigh signal levels of time compressed clutter energy. Also, in pulsecompression systems having a large compression ratio, if clutterrejection is implemented after pulse compression the clutter recognitioncircuits may be energized by time side lobes from large real targets.Further, the conventional approach of pulse compression prior'to cluttercancellation can cause a reduction in the systems sensitivity to realtargets, due to the constant false alarm rate action inherent in somepulse compression circuits; For example, in the case of prior art singlelevel 180 phase coding) digital pulse compression systems operating inextended clutter, such as caused by rain, target signals embedded inclutter would be suppressed by the pulse compression processing; and theinput clutter level would not cause a detectable rise in the decodedoutput level.

SUMMARY OF THE INVENTION According to one preferred embodiment of thesubject invention, a moving target signal processor is provided which isadapted for use in a pulse compression, scanning type radar. Theprocessor comprises a plurality of clutter canceller units each of whichhave different clutter cancellation characteristics that are a functionof the number of consecutive transmissions occurring at any given scanlocation. A clutter detection circuit provides alarm signals indicativeof the clutter energy content in the uncompressed received'radar signaland in the uncompressed output signals from each of the canceller units.A logic circuit responds to the alarm signals and to the number of priortransmissions at the given scan location, to control the radar such thatthe clutter energy content of the processors output signal is below apreselected level.

It is therefore an object of the subject invention to provide a movingtarget signal processor which automatically adapts its level of MTIoperation to the clutter environment so as to maintain the clutterenergy content in its output signals below a preselected level,

while minimizing the radar time required at each scan location.

Another object is to provide an MTI pulse compression system in whichclutter signals are detected and v type of MTI processing required tominimize the radar time while maintaining an acceptable level of clutterenergy content in the processor's output signals.

DESCRIPTION OF THE DRAWINGS The novel features of this invention as wellas the invention itself will bebetter understood from the accompanyingdescription taken in connection with the accompanying drawings, in whichlike reference characters refer to like parts and in which:

FIG. 1 is a block diagram of a radar system incorporating a movingtarget signal processor in accordance with the subject invention;

FIG. 2 is a block diagram of one preferred embodiment of a moving targetsignal processor in accordance with the invention;

FIG. 3 is a block diagram showing the clutter detection circuits of theprocessor of FIG. 2 in greater detail;

FIG. 4 is a block diagram of an up-down counter'suit able for use in thedetection circuits of FIG. 3;

FIGS. 5, 6, 7 and 8, are block diagrams of a timing signal circuit, aclutter gate circuit, a ring counter, and a clutter gate counter,respectively, suitable for use in the clutter detection circuits of FIG.3;

FIGS. 9 and 10 are block diagrams showing the PRF sequence counter, andlogic control circuitry, respectively, of FIG. 2 in greater detail;

FIGS. 11, 12, and 13 are block diagrams of suitable mechanizations-forthe alarm flip-flop circuits of FIG.

FIG. 14 is a block diagram of a gating arrangement implementation of theselection circuit shown in FIG. 2; and

FIG. 15 is a block diagram of logic circuits for controlling the gatesshown in FIG. 14.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The direction of thetransmitting and receiving beams of antenna 55 is controlled by a scanposition controller 56. Antenna 55 may be of the electronic scan 'typein which the relative phase of the signals applied to'the individualarray elements is controlled by scan position controller '56. Systemcomputer 57 controls the scan position unit 56 so that the antenna beamis directed in accordance with a preprogrammed pattern. As will bedescribed subsequently, the number of consecutive transmission at anygiven scan location is determined by MTI processor 58. Computer 57 alsoprovides timing and synchronization pulses to transmitter 53 andprocessor'58.

Reflected energy received by antenna 55 is applied through duplexer S4and is heterodyned in a mixer 59 to provide an IF signal representativeof the received radar energy. This IF signal is processed within an IFamplifier 60 and is then applied to MTI processor 58.

In accordance with one embodiment of the invention, transmitter 53provides a relatively long, phase encoded output pulse; and processor 58after first detecting and reducing clutter energy, if any is present inthe received IF signal, then compresses or decodes the resultingsignals. For example, the transmitted pulse may be 31 times longer thanthe compressed range bins, hereinafter simply referred to as range bins,to effect a pulse compression gain of db for point source targets. I

As mentioned above, the features of the subject invention which provideclutter recognition and reduction prior to pulse compression, avoidserious limitations inherent with most prior art systems. For example,clutter reduction prior to pulse compression greatly reduces the dynamicrange requirements on processor circuits; and clutter detection on highrange side lobes of large real targets is avoided. Also signal detectiondegradation due to target signal suppression by clutter during pulsecompression is reduced by the processing techniques of the invention.

A utilization device 61 is coupled to the output circuit of processor 58and is adapted for further process ing the output signals therefrom.Utilization device 61 may include, for example, a display system or atarget tracking computer.

Reference is now directed primarily to FIG. 2 which shows one preferredembodiment of a moving target signal processor in accordance with theinvention. As shown in the lower central portion of FIG. 2, the IFsignal from amplifier 60 (FIG. 1) is applied to an amplitude detector 73and the output signal therefrom, designated RV for raw video, is appliedto one input channel of a clutter detection circuit 74. The IF receivedsignal from amplifier 60 (FIG. 1) is also applied through a delay unit75; and is then applied in parallel to an amplitude detector 77, and aphase detector 78.

As will be explained subsequently, unit 75 provides the proper timedelay to compensate for the time lag inherent in providing clutter gatesignals indicative of clutter in the uncompressed received signals. Theclutter gate signals may be used, for example, to control a clutterlocking" circuit such as described and shown in section 9.4 of the textRadar Design Principles, by Fred E. Nathanson, McGraw-Hill Book Company,New York, New York.

The delayed IF signals from unit 75 are processed in phase detector 78with the COHO reference signal from unit 50 of FIG. 1; and the resultingoutput signals are applied to an A to D converter 82. The digital outputsignals from converter 82 are'processed in an MTI first canceller 83 andthen in a second canceller 84.

It is noted that in the interest of maintaining the clarity of thedrawings a single composite lead such as lead 85, for example, is shownfor applying multiple bit digital signals. Also a single channel isshown for the phase detected video from unit 78 through second MTIcanceller 84; although, preferably complex units for processing inphaseand quadrature signals are usedto avoid the 3 db loss in sensitivityencountered insingle channel systems. Additionally, timing signals, suchas clock pulses, are provided to all digital units from computer 57v(FIG. l) for the synchronization of these units. The application of theclock pulses is not illustrated in the drawings nor included in thefollowing logic equations so as to maintain the clarity of the drawingsand description. However, it is understood that all digital operationsoccur only in coincidence with a clock pulse.

Still primarily considering FIG. 2, the output signals from cluttercanceller units 83 and 84, designated lCV for first canceller video, and2CV for second canceller video, respectively, are applied to clutterdetection circuit 74. In response to the lCV, 2CV and raw video signals,as well as to PRF count signals applied from sequence counter 86,detector 74 provides alarm signals and the clutter gate signal. Thealarm signals are representative of whether or not the clutter energycontent of the raw video, the lCV and the 2CV signals, respectively, isless than a predetermined level. The number of transmissions which haveoccurred at a given scan location, as indicated by the PRF count, isutilized to insure that the output signals from the canceller units havehad time to build up to an effective operating level prior to theiranalysis for clutter content.

In response to the alarm signalsand to the PRF count, a logic controlcircuit 87 provides command signals to computer 57 (FIG. 1), to causeadditional transmissions at any given scan location until the cluttercontent of one of the raw video, the lCV or the 2CV signals is withinpreselected limits. In the event that after a predetermined number oftransmissions none of these just mentioned signals have an acceptablelevel of clutter energy content, then logic control circuit 87 commandsa pulse doppler burst of from 12 to 20 transmissions, for example. Thecommand signal applied from logic control circuit 87 tocomputer 57 maybe used therein, for example, to enable an inhibit gate which interruptsthe antenna scan sequence for the next transmission period. Hence thenext transmission will be at the same scan location each time an outputsignal is provided by logic control circuit 87.

The clutter gate signal, designated CG, produced by clutter detectorcircuit 74 indicates the presence of clutter energy in the uncompressednondelayed raw video. As will be explained subsequently, unit may have atime delay equal to 37 range bins, for example, to allow for the timelag of detection circuit 74 in detecting the presence of clutter in rawvideo; whereby thesignals from unit 75 are in time synchronism with theclutter gate signal.

The delayed raw video from A to D converter 94, as well as the lCV and2CV signals are applied to a selection circuit 90. In response-to the.alarm signals from clutter detection circuit 74 and to the PRF countsignals, the selectioncircuit couples the input channel which has anacceptable clutter energy content to a digital pulse compression unit91. If, however, after a predetermined number of range sweeps at thesame scan location none of the input signals to selection circuit 90 areacceptable, then the 2CV signals are applied through circuit 90, pulsecompressor 91 and gate 88 to a digital pulse doppler processor 76. TheMTI processed, and pulse compressed output signal from unit 91 isapplied through switch 89 to utilization device 61 of FIG. 1, if one ofthe signals applied to selection circuit 90 has an acceptable clutterenergy content during the predetermined number of range sweeps.Otherwise, following the processing interval of doppler processor 76,the output therefrom is applied through switch 89 to utilization device61. It is noted that when operating in a clutter environment there willbe interpulse periods in which none of the signals applied to theselection circuit have acceptable clutter energy content, and duringthese interpulse periods the selection circuit will not provide anoutput signal.

An example of a suitable MTI canceller for units 83 and 84 is thedigital equivalent of the circuit shown in FIG. 9.7(a) on page 328 ofthe above cited Radar Design Principles" text. It is again noted thatthe clutter canceller is preferably mechanized in the dual (inphase andquadrature components) phase configuration.

Digital pulse doppler processor 76 of FIG. 2 could be, or example, ofthe type shown in FIG. 14-17 on page 590 of the above referenced text.The digital equivalent of the circuit of FIG. 12-7 on page 470 of thisRadar Design Principles book would be suitable for pulse compressor 91;and transmitter 53 (FIG. 1) would then include suitable conventionalcircuitry (not shown) for 180 degree phase encoding on alternate rangebins of each transmitted pulse.

Reference is now directed primarily to FIG. 3 which depicts thedetection circuit 74 of FIG. 2 in greater detail. As there shown a firstchannel 62 for processing the raw video (RV) includes a thresholdcircuit 63, an updown counter 64, a clutter gate 65, a ring counter 66,a clutter gate counter 67, and an alarm flip-flop 68.

The threshold level of threshold circuit 63 is selected as low aspossible without causing excessive clutter false alarms; for example, 3db above rms receiver noise level. The output signal of thresholdcircuit 63, designated 6,, is a logical 1 when the threshold level isexceeded and a logical 0 when the raw video is less than the thresholdlevel. The voltage levels corresponding to the logical l and logical 0conditions may be any two distinctive voltage levels which areconvenient for mechanizing the logic equations presented hereinafter.

The output signal of threshold circuit 63 (G is ap-' plied to up-downcounter 64 which counts up one count in response to a 1 level inputsignal and counts down one count for a 0 input signal. With a knownstatistic for the input signal, this type of counter is a very simpleform of a Markov processor. The expected value in counter 64 will beclose to zero when only receiver noise is being processed. For the abovedescribed system in which the transmitted pulse extends over 31compressed range bins, for a large amplitude real target counter 64would nominally count up to 31; and then count down towards zero whenthe target signal ceases. However, with a 3 db threshold level there isa false alarm rate due to thermal (receiver) noise on the order of 0.13,for example; and hence there is some probability that the counter willcount beyond 31 in response to a single target. The below equation givesthe probability of at least r noise false alarms in 11" samplingperiods; and Table I tabulates the probability of a given number ofnoise false alarms out of various groups of sampling periods.

II n E (OPT- 5:!

TABLE I P,,,(r/n) probability of r noise false alarms out of n samplesP, (2/2) 0.13 0.017 probability of 2 successive noise false alarms P,(6/6) 0.13 4.8 X I0 probability of 6 successive false alarms The sum ofthe cases from P, (6/6) to P,,,( 1 3/20) defines an upper bound of l.5lX l0 which is the probability of a single target (31 range bins) causinga clutter gate detection when the clutter recognition threshold ofclutter gate 65 is set at 37, Le. six more than nominally expected froma single target.

The count of counter 64 in response to thermal noise only, can bedetermined by computing the nth power of the probability matrix whichdescribes the counter; and the probability of receiver noise aloneexceeding the clutter recognition threshold is insignificantly small.

Two thresholds are used on the clutter gate circuit 65. First a count of37 has been selected, corresponding to a false alarm on large targets of1.5 X l0", to initiate clutter gate detection. The up-down counter 64 ismechanized so as not to allow a count above 37 in extended clutter; andthe clutter gate detection is deenergized when the counter drops below acount of 10, which is the expected count 37 range bins after cluttersignals have terminated. It will be recalled from the description ofFIG. 2 that the IF received signals applied to the canceller units 83and 84 are delayed 37 range bins. This allows the clutter gate providedby channel 62 to be in time alignment with the data processed by clutterlocking circuits (not shown). The clutter gate signal (CG) is applied toring counter 66.

For the above-described example wherein the transmitted pulse has a timeduration equal to 31 range bins (clock pulse periods), ring counter 66is mechanized to count up to 31, reset, and repeat the counting andresetting cycle during the total time period that clutter gate circuit64 provides a CG output signal.

The clutter gate counter 67 senses each time ring counter 66 passesthrough the count of 3 l and counts up by one in response thereto.Therefore the count held by counter 67 is indicative of the number ofgroups of 31 range bin increments, on any given range sweep, thatcontained clutter. As used herein the term range sweep means thatportion of the receiving period following each transmission, from whichthe received energy is processed. When counter 67 reaches a preselectedthreshold count, for example 3 to 10 depending on the systemapplication, flip-flop 68 is-set, thereby providing an A alarm signal.

Channels 69 of FIG. 3 processes the lCV signal from first cluttercanceller unit 83 of FIG. 2 in a manner similar to that described abovefor channel 62 and the RV signals. The respective units of channel 69have been assigned reference numerals having the same units and tenthsdigits of the corresponding units of channel 62 except that thereference numerals for channel 69 are in the 100 series. Similarlychannel processes the 2CV signals from the second clutter canceller; andrespective units thereof have been assigned reference numeralscorresponding to their counterparts in channel 62, except that they arein the 200 series.

The A alarm signal from flip-flop 68 is sensed at the end of the rangesweep, and one clock time later flipflop 68 as well as all counters, arereset to allow the data from the next range sweep to be processed in asimilar manner.

During the second range sweep initiated at the same scan location by theA alarm signal, channel 69 operates to observe the clutter residue inthe output signal from first clutter canceller 83. If this clutterresidue extends over too large of a range interval, flip-flop circuit168 generates a B alarm signal effective to order a third transmission.During the third range sweep both the output signals from the first andthe second MTI cancellers will be sensed. If the radars PRF (pulserepetition rate) is such as to provide a 60 mile range sweep, forexample, then clutter signals from the first ambiguous range interval(60 to 120 miles) may be received. In such an event a C alarm signal maynot be generated after the third range sweep but a D alarm indicative ofthe output signal from the second clutter canceller may be produced.Consequently, the output signal from the first canceller unit would beselected for further processing. Alternatively, if the clutter spectrumis wide due to rain or chaff, for example, during the third range sweepa C alarm signal would be generated but not a D alarm, in which case theoutput from the second can celler would be selected. Flip-flop circuits268 (FIG. 3) also provide an E alarm signal indicative of the clutterresidue from the second canceller, during the first ambiguous rangeinterval (fourth range sweep) exceeding the preselected value. The Ealarm signal is effective to command the into an MTI-range gated pulsedoppler mode which may require from 12 to 20 transmissions, for example;depending on the number of doppler filters implemented in the pulsedoppler processor. The rationale underlining the above describedautomatic selection of the proper level of MTI operation is as outlinedbelow.

1. No clutter MTI not used, delayed raw video used for processors outputsignal.

2. Moderate land clutter single MTI canceller used.

3. Large amount of land clutter double MTI canceller used.

4. Moderate rain or chaff double MTI canceller used.

5. Heavy rain or chaff MTI range gated pulse doppler processor used.

As indicated above, PRF sequence counter 86 (FIG. 2), provides anindication of the number of consecutive range sweeps which have takenplace at a given scan location; and this PRF count signal is used inconjunction with the alarm signals for selecting the signal appliedthrough selection circuit 90. A summary of the logic for selection ofthe signals applied to pulse compressor 91, as well as for controllingthe number of transmissions per scan position, is outlined in Table IIbelow.

TABLE II Range Sweep At State of Same Scan Location Alarm F/F's A ordera second transmission K MTI not required use first MTI canceller outputAB order another transmission use first MTI canceller output ABCD usesecond MTI canceller output ABCQ order another transmission 4 ABCDEr usesecond MTI canceller output ABCDE order pulse doppler burst Theoperation of the subject invention may be better understood by aconsideration of the mechanization of the units comprising channel 62 ofFIG. 3. A suitable mechanization for up-down counter 64 is shown in FIG.4 as comprising six flip-flops (F/F) designated 1 through 6 with F/F-lproviding the least significant digit (LSD) of the counter's outputsignal, and F/F-6 supplying the most significant digit (MSD).

In order to maintain the clarity of the drawings, in lieu of showing amaze of AND/OR gates, the organization of which is well known by thoseskilled in the art, the logic equations defining the signals utilized tocontrol the set and reset input terminals of the various F/F circuitsare shown on the drawings adjacent to the terminals. In these logicequations the logical OR operation is indicated by a sign between termsor groups of terms; and the logical AND operation by the absence of asymbol between terms or groups of terms. To further clarify thesymbology adopted herein, the AND I and OR gate implementation for thesignal applied to the set input terminal of F/F-l is shown in FIG. 4, ascomprising OR gates 101 and 103; and AND gates 102, I04 and 105.

The term G shown in FIG. 4, is the output signal from threshold circuit63 (FIG. 3) and is a logical 1 when the applied raw video (RV) signalexceeds the preselected threshold level. The signal F is designated thedead time trigger" and is provided by the circuit shown in FIG. 5.

Referring momentarily to FIG. 5, F/F-8 is set by the trigger pulse tapplied from system computer 57 (FIG. 1). Trigger pulse r is indicativeof the end of the active ranging time period following eachtransmission, i.e., the end of the range sweep. The signal F from the Qoutput terminal of F/F-8 is applied to the reset input terminal thereof,whereby the F/F is reset during the first clock pulse after it is set.As mentioned previously to maintain the clarity of the drawings, theapplication of clock pulses is not shown nor included in the logicequations. However, it is understood that all .digital operations occurin synchronism with clock pulses provided by system computer 57 (FIG.I), for example.

Still considering FIG. 5 a delayed dead time trigger F is provided byF/F-9 which is set in response to the signal F F applied from AND gate106; and is reset on the following clock pulse by the signal F appliedto the reset input terminal thereof.

Returning now to the description of the up-down counter 64 shown in FIG.4, the counter counts up one count each clock pulse period in which thesignal RV exceeds the threshold level of unit 63, that is, in responseto a signal G being produced by unit 63. The counter counts down onecount during each clock pulse period during which a signal G is notapplied. The counter is limited to a preselected maximum count such as37, for example, and to a preselected minimum count such as O, forexample. The maximum count feature maintains the statistical validity ofthe clutter detection following operations in extended clutter. Also, itis noted that the counter is reset at the end of each range period bythe dead time trigger signal F F/F-7 shown in FIG. 6 mechanizes cluttergate 65 of FIG. 3. In the selected embodiment F/F-7 is set on the countof 37 and provides the signal F which is the same as the clutter gatesignal (CG) indicated in FIG. 3. F/F-7 is reset at a count of or at theend of each range sweep. As mentioned previously the count value atwhich the clutter gate F/F-7 is set is determined by the statisticalnature of the signals and the systems application. For example, in apulse compression system having a 31 to 1 pulse compression ratio, aclutter threshold level of 37 implies that a large target signal wouldhave to be encompassed by 6 noise false alarms to produce an erroneousclutter gate indication. The lower threshold of 10 for resetting F/F-7is selected statistically as an indication that the clutter content inthe received signal has vanished.

FIG. 7 illustrates one suitable mechanization for ring counter 66; andas there shown the ring counter comprises five F/Fs designated 10through 14, with F/F-10 providing the least significant digit of thecounters output signal, and F/F-l4 supplying the most significant digit.Ring counter 66 operates to count the number of sets of 31 clock pulseseach, which occur during the presence of clutter gate signal, i.e.during the time interval F/F-7 is set. To rephrase this last point in aslightly different manner, during the time periodof the clutter gatesignal, counter 66 counts clock pulses up to the count of 31 and thenresets and repeats the counting sequence. Hence the ring counters countis indicative of the number of uncompressed ranging intervals (31 rangebins) during which clutter energy has been detected.

Clutter gate counter 67 is shown in FIG. 8 as comprising F/F- through 24and AND gate 110. Gate 1 10 provides an output signal G when the ringcounter 66 reaches a count of 31. F/F -20 provides the least significantdigit of the clutter gate counters output signal, and F/F-23 providesthe most significant digit.

The implementation of the up-down counter, clutter gate, ring counterand clutter gate counter for channels 69 and 70 of FIG. 3 could beidentical to that described hereinabove relative to channel 62; andcorresponding F/Fs and the output signals provided thereby could beassigned corresponding numerical reference designations in the 100 and200 series respectively. For example, the least significant digit ofclutter gate counter 167 (FIG. 3) would be the signal F and for counter267 it would be F FIG. 11 shows the mechanization of A alarm F/F-68which provides an output signal indicative of clutter detection on theraw video signal. FIG. 12 depicts the mechanization of alarm F/Fs 168associated with channel 69 of FIG. 3, with F/F-B providing an alarmsignal indicative of clutter detection in the output signal of the firstcanceller unit during the second or succeeding range sweeps; and F lF-Cproviding an output alarm signal indicative of clutter detection in thefirst clutter cancellers output signal during the third or succeedingrange sweeps. FIG. 13 illustrates the mechanization of alarm F/F-268associated with channel 70; with F/F-D providing an alarm output signalindicative of clutter detection in the output signal from the secondclutter PRF sequence counter 86 of FIG. 2 is shown in greater detail inFIG. 9 as comprising F/F-30 through 33, with F/F-30 providing the leastsignificant digit of the output signal and F/F-33 the most significantdigit. The signal G utilized in the mechanization of the PRF sequencecounter is indicative of the end of an MTI sequence at a given scanlocation. This signal G is generated by logic control circuit 87 (FIGS.2 and 10).

Logic control circuit 87 is shown in greater detail in FIG. 10 ascomprising an .arrangement of AND gates 111 through 116 and OR gates 117and 118 for providing the signal G AND gate 119 senses the signal Gapplied from inverter 120, at the delayed dead time trigger (F periodand sets a F/F-35 in response thereto. The output signal from F/F-35, Fis applied to system computer 57 (FIG. 1) which in response theretocommands the radar system to provide an additional transmission at thesame scan location (inhibits an advance of the scan sequence). F/F-36senses an E alarm signal during the fourth range sweep at any given scanlocation to provide the signal F which locks the system in the pulsedoppler mode. As mechanized in the illustrated embodiment, F/F-36 isreset after the occurrence of 12 range sweeps at the given scanlocation. However, the number of range sweeps comprising a doppler burstis a function of the number of doppler filters mechanized in the dopplerprocessor 76 (FIG. 2) and of the systems application. Further, it iswithin the scope of the invention to mechanize an adaptive number ofrange sweeps for the doppler burst as a function of the content of theclutter gate counter, such as counter 267 of channel 70 (FIG. 3).

canceller during the third and succeeding range sweeps; and F/F-Eprovides an output signal indicative of clutter detection in the outputsignal from the second clutter canceller during the fourth andsucceeding range sweeps.

In the implementation of the alarm circuits of FIGS. 11 through 13 acount of three in the associated clutter gate counter is sensed as aclutter alarm indication. However, the alarm threshold valve, i.e., thenumber of sets of uncompressed range bin intervals (31 clock pulseperiods) during which clutter must be detected to provide a clutteralarm indication will vary as a function of the system s application.Also the clutter threshold level need not be selected at the same valuefor the various channels.

Referring now to FIG. 14 which shows the selection circuit (FIG. 2) ingreater detail, storage registers through 127 store one range sweep ofdata from the raw video, first clutter canceller, and second cluttercanceller channels, respectively. Gates 128 through 131, when enabled,couple the signals applied thereto, to digital pulse compression circuit91 (FIG. 2).

The circuits for enabling the proper one of the gates 128 through 131,mechanized in accordance with the logical operations indicated in TableII above, are shown in FIG. 15. It is noted that the selection circuit90 only applies signals to pulse compressor 91 from range sweeps inwhich one of the channels had less than a preselected maximum clutterenergy content; or during the pulse doppler mode, as mechanized by gate131.

F/F-40 of FIG. 14 is set during the dead time trigger period (Ffollowing each range sweep if an A alarm signal has not been generatedand if the system is not locked in the pulse doppler mode, as indicatedby the F signal. The signal from the Q output terminal of F/F-40triggers an F/F-l35 which provides an output signal RVD-G to gate 128 ofFIG. 14. F/F-35 is reset on the next range sweep by the F signal, andhence provides an output pulse of one range sweep duration, whereby onerange sweep of data is shifted out of register 125 into digital pulsecompressor 91. If after the second range sweep at any given scanlocation, i.e. a

PRF count of one at time F an A alarm is present, but a B alarm is not,then F/F-41 applies a trigger signal through an OR gate 136 to aF/F-127. It is noted that the PRF count is one at the F time period ofthe second range sweep, due to the mechanization of PRF sequence counter86 in which the counter is incremented during the delayed dead timeperiod (F The F/F-137 provides an output signal designated lCV-G whichenables gate 129 of FIG. 14 whereby one range sweep of data is shiftedout of register 126 into pulse compressor 91. Also if following thethird range sweep A and B alarm signals are present but a C alarm isnot, the output signal from F/F-42 is applied through OR 136 to triggerF/F-137. F/F-137 is reset one range sweep period, after being set, bythe F signal. Hence, the 1CV video is gated to pulse compressor 91 if aB alarm signal is not produced during the second range sweep or if a Calarm signal is not produced during the third range sweep.

An F/F-43 is set following the third range sweep if A, B and C alarmsare present but a D alarm is not, and the output signal from F/F-43 isapplied through an OR gate 138 to an F/F-139. The output signal fromF/F- 139, designated 2CV-G is applied to gate 130 of FIG. 14 and inresponse thereto one range sweep of data is transferred from register127 to pulse compressor 91. Also, if following the fourth range sweep A,B, C and D alarms are present but an E alarm is not, F/F-44 is set andits output signal is applied through OR gate 138 to trigger one F/F-l39.Hence the 2CV signals from register 127 are applied through gate 130 topulse compressor 91 if a D alarm is not indicated following the thirdrange sweep, or if an E alarm signal is not present following the fourthrange sweep. Further, 2CV signals are applied through gate 131 duringthe pulse doppler mode of operation.

As explained above, if an E alarm signal is produced during the fourthrange sweep, the system is locked in a pulse doppler mode for apredetermined number of range sweeps; and during this period selectioncircuit 90 applies the 2C\/ signals through pulse compressor 91 and gate88 (FIG. 2) to pulse doppler processor 76. After the pulse dopplerprocessing period, the range gated output signals of the dopplerprocessor are applied through switch 89 (FIG. 2) to utilization device61. Switch 89 is mechanized so that in the absence of the DV-G signalthe output from pulse compressor 91 is coupled to utilization device 61;and during the period the DV-G signal is applied, the output of dopplerprocessor 76 is coupled to utilization device 61. During the pulsedoppler mode pulse compressor 91 processes 2CV signals having anunacceptable level of clutter energy; however, significant clutterenergy had previously been removed therefrom by the first and secondcanceller units, so excessive dynamic range is not required in the pulsecompressor circuits.

The signal DV-G is provided by F/F-45 and F/F-140 of FIG. 15. F/F-45 isset at the F time period at the end of the pulse doppler mode; and theoutput signal therefrom triggers an F/F-140 which is reset by the Fsignal of the following range sweep. The output signal of F/F- 140enables switch 89 (FIG. 2) for a sufficient time period to allow therange gated output signals of doppler processor 76 to be applied toutilization device 61.

To summarize the operation of the moving target processor in accordancewith the invention, the clutter canceller units 83 and 84 have differingclutter cancellation characteristics which are a function of the numberof consecutive range sweeps occurring at any given scan location.Clutter detection circuit 74 (FIG. 2) is coupled to data channelsassociated with the range video and the first and second cancellerunits; and provides alarm signals indicative of whether the respectivedata signals (not yet range compressed) have less than a predeterminedclutter energy content. The alarm sig nals, in conjunction with the PRFcount, are processed by logic control circuit 87 to determine if any ofthe data signals is acceptable. If an acceptable signal is present, theassociated channel is coupled through selection circuit 90, digitalpulse compressor 91, and switch 89 to utilization device 61, and theradar system is allowed to continue in its normal scanning sequence.However, if none of the data channels have an output signal withacceptable clutter content, then the radar is commanded to provide anadditional transmission at the same scan location. Following the secondtransmission the data channels are again examined as to clutter contentand if an acceptable output signal is sensed, it is coupled to theutilization device. If following the second range sweep period anacceptable output signal has not been produced, the radar is againordered to provide another transmission at the same scan location. Thissequence is repeated until the output signals from one of the datachannels is acceptable or until a predetermined number of transmissionshave taken place at the same scan position. This predetermined numbermay be equal to the number of range sweeps required for the secondcanceller to build up to its effective state, for example. After thepredetermined number of transmission without an acceptable signal beingproduced, the processor locks the system into a pulse doppler mode and arelatively large number of range sweeps at the same scan location areprocessed by pulse doppler processor 76.

In the above described preferred embodiment only two clutter cancellerunits and one doppler processor unit are shown to illustrate theprinciples of the invention. However, it will be readily apparent tothose skilled in the art that the scope of the subject invention is notrestricted in any way to the number of clutter rejection unitsmechanized; but is adaptable to any number and type of such units. Themodifications for clutter detection circuit 74, logic control circuit 87and selection circuit 90 in accordance with the teachings of thisinvention, so as to accommodate various arrange ments of cancellerunits, will be readily apparent to those skilled in the art. Also itwill be apparent that only a single channel of the clutter detectorcircuit, such as channel 62 could be used for applications wherein onlyclutter detection and/or a clutter gate signal are required.

Hence there has been described a novel and improved moving targetprocessor in which clutter reduction is performed prior to pulsecompression; and wherein the clutter energy content of the outputsignals therefrom is held below a preselected value regardless of theclutter environment, and with the minimum of radar time.

What is claimed is:

l. A moving target signal processor for use with a scanning type energytransmission and reception system, said processor comprising:

a plurality of clutter canceller units each adapted for processingsuccessive range sweeps of received signals and having differing cluttercancellation characteristics which are a function of the number of rangesweeps of received signals from the same scan location processedthereby; and

means for sensing the clutter energy content in said received signalsand in the output signals of said clutter canceller units, and forcommanding additional transmissions at the same scan location, if duringthe current range sweep period the clutter energy content of saidreceived signals and the output signals from said clutter cancellerunits is in excess of predetermined amounts.

2. The processor of claim 1 wherein said means for sensing clutterenergy and for commanding additional transmissions includes:

clutter detection means for providing alarm signals during each rangesweep period, which are indicative of clutter energy content in excessof said predetermined amounts in said received signals and in the outputsignals of said clutter canceller units, respectively, and

logic control means responsive to said alarm signals,

for providing control signals for commanding additional transmissions atthe same scan location, if during the current range sweep period theclutter energy content of said received signals and the output signalsfrom said clutter canceller units is in excess of said predeterminedamounts.

3. The processor of claim 2 wherein said clutter detection meansincludes means for providing an alarm signal associated with any givenclutter canceller unit only during selected range sweep periods in whicheffective output signals of reduced clutter content can be provided bysaid any given clutter canceller unit, said selected range sweep periodsbeing predetermined as a function of the characteristics of said givenclutter canceller unit.

4. The processor of claim 1 further comprising a signal output terminal;and selection means for determining if said received signals or one ofsaid output signals from said clutter canceller units has less than saidpredetermined amounts of clutter energy, and for applying said signalswith less than said predetermined amount of clutter energy to saidoutput terminal.

5. The processor of claim 3 further comprising a signal output terminal;and selection means for determining if said received signals, or one ofsaid output signals from said clutter canceller units during therespective selected range sweep periods associated with each of theclutter canceller units, has less said predetermined amounts of clutterenergy, and for applying said signal with less than said predeterminedamount of clutter energy to said output terminal.

6. The processor of claim 1 further including a doppler processor unit;and means for commanding a pulse doppler burst of successivetransmissions, if the clutter energy content of said received signalsand the output signals from said clutter canceller units is in excess ofsaid predetermined amounts during a predetermined number of range sweepperiods at the same scan location.

7. The processor of claim 5 further comprising a doppler processor unit;and means for commanding a pulse doppler burst of successivetransmissions if the clutter energy content of said received signals andthe output signals from said clutter canceller units during therespective selected range sweep periods associated with each of theclutter canceller units, is in excess of said predetermined amounts,during a predetermined number of range sweep periods at the same scanlocation.

8. The processor of claim 7 including means for sensing the completionof the pulse doppler burst and for then coupling the output of saiddoppler processor to said output terminal.

9. The processor of claim 2 adapted for use with a pulse compressiontype scanned energy transmission and reception system; and wherein saidclutter detection means includes counter means for staticallydetermining during each range sweep period if clutter energy content inexcess of predetermined amounts is present in the uncompressed receivedsignals and in the uncompressed output signals of said canceller units.

10. The processor of claim 9 wherein said counter means includes aplurality of processing channels, each of vwhich is coupled to receivesaid received signals or the output signals from one of said cluttercanceller units, and including: a threshold circuit for providing anoutput signal during range bin intervals in which the signals applied tosaid channel exceeds a threshold level;an up-down counter mechanized tocount up towards a preselected maximum count during each range bininterval in which an output signal is provided by said thresholdcircuit, and for counting down towards a preselected minimum countduring each range bin interval in which an output signal is not providedby said threshold circuit; and alarm means responsive to the count ofsaid up-down counter for providing an alarm signal indicative of aclutter content in the applied signals in excess of said predeterminedamount.

11. The processor of claim 10 further comprising a signal outputterminal; and selection means for determining if said received signal orone of said output signals from said clutter canceller units has lessthan said predetermined amounts of clutter energy, and for applying saidsignal with less than said predetermined amount of clutter energy tosaid output terminal.

12. The processor of claim 11 further comprising a pulse compressor unitcoupled to said signal output terminal for processing said signal havingless than said predetermined amount of clutter energy content, so as toprovide signals compressed in the range dimension.

13. The processor of claim 10 wherein said alarm means includes cluttergate counter means for counting range bin intervals, during a cluttergate interval start ing when the count of said up-down counter isgreater than a first number, and ending when the count is less than asecond number; and means for providing said alarm signal in response tothe count of said clutter gate counter means.

14. The processor of claim 13 wherein said clutter gate counter meansincludes a clutter gate circuit for providing a clutter gate signalduring said clutter gate interval; a ring counter enable by said cluttergate signal for providing an output signal indicative of a group of apredetermined number of range bins having occurred during said cluttergate interval; and a clutter gate counter circuit for counting thenumber of said group of range bins occurring each range sweep period;and said alarm means includes an alarm logic circuit adapted to providean alarm output signal when the count of said clutter gate countercircuit exceed a selected value.

15. The processor of claim 14 wherein said alarm means includes meansfor inhibiting the generation of said alarm output signal except duringselected ones of the range sweeps at the same scan location.

16. A moving target signal processor for use with a scanning, pulsecompression type energy transmission and reception system, saidprocessor comprising:

a plurality of clutter canceller units each adapted for processing rangesweeps of uncompressed received signals;

clutter detection means for statically determining during each rangesweep if clutter energy content in excess of predetermined amounts ispresent in said uncompressed received signals and in the output signalsof said clutter canceller units, respectively; and

logic control means coupled to said clutter detection means forcommanding an additional transmission at the same scan location ifduring the current range sweep the clutter energy content of saidreceived signals and the output signals from said clutter cancellerunits is in excess of said predetermined amounts.

17. The processor of claim 16 further comprising a signal outputterminal; and selection means coupled to said clutter detection meansfor determining if said received signals or if one of said outputsignals from said clutter canceller units has less than saidpredetermined amount of clutter energy, and for applying said signalswith less than said predetermined amount of clutter energy to saidoutput terminal.

18. The processor of claim 17 further comprising a pulse compressor unitcoupled to said signal output terminal for processing said signalshaving less than said predetermined amounts of clutter energy, so as toprovide time compressed output signals having less than saidpredetermined amount of clutter content.

19. The processor of claim 17 further comprising a doppler processorunit; and said logic control means includes means for providing adoppler command signal for commanding a pulse doppler burst ofsuccessive transmissions if the clutter energy content of said receivedsignals and the output signals from said clutter canceller units is inexcess of said predetermined amounts during a predetermined number ofrange sweep periods at the same scan location.

20. The processor of claim 19 wherein said selection means includesmeans for sensing the completion of the pulse doppler burst and for thencoupling the output of said doppler processor to said output terminal.

21. The processor of claim 16 wherein said clutter detection meansincludes counter means for statically determining during each rangesweep period if clutter energy content in excess of predetenninedamounts is present in the uncompressed received signals and in theuncompressed output signals of said canceller units.

22. The processor of claim 21 wherein said counter means includes aplurality of processing channels, each of which is coupled to receivesaid received signals or the output signals from one of said cluttercanceller units, and including: a threshold circuit for providing anoutput signal during range bin intervals in which the signals applied tosaid channel exceeds a threshold level; an up-down counter mechanized tocount up towards a preselected maximum count during each range bininterval in which an output signal is provided by said thresholdcircuit, and for counting down towards a preselected minimum countduring each range bin interval in which an output signal is not providedby said threshold circuit; and alarm means responsive to the count ofsaid up-down counter for providing an alarm signal indicative of aclutter content in the applied signals in excess of said predeterminedamount.

23. The processor of claim 22 wherein said alarm means includes cluttergate counter means for counting range bin intervals during a cluttergate interval starting when the count of said up-down counter is greaterthan a first number, and ending when the count is less than a secondnumber; and means for'providing said alarm signal in response to thecount of said clutter gate counter means.

24. The processor of claim 23 wherein said clutter gate counter meansincludes a clutter gate circuit for providing a clutter gate signalduring said clutter gate interval; a ring counter enabled by saidclutter gate signal for providing an output signal indicative of a groupof a predetermined number of range bins having occurred during saidclutter gate interval; and a clutter gate counter circuit for countingthe number of said group of range bins occuring each range sweep period;and said alarm means includes an alarm logic circuit adapted to providean alarm output signal when the count of said clutter gate countercircuit exceed a selected value.

25. A device for detecting clutter energy in the received signals from apulse compression type energy transmission and reception system, saiddevice comprising:

a threshold circuit for providing an output signal during range binsintervals in which the received signals exceeds a threshold level;

an up-down counter mechanized to count up towards a preselected maximumcount during each range bin interval in which an output signal isprovided by said threshold circuit, and for counting down towards apreselected minimum count during each range bin interval in which anoutput signal is not provided by said threshold circuit; and

alarm means responsive to the count of said up-down counter forproviding an alarm signal indicative of a clutter content in the appliedsignal in excess of a predetermined amount.

26. The device of claim 25 wherein said alarm means includes cluttergate counter means for counting range bin intervals, during a cluttergate time interval starting when the count of said up-down counter isgreater than a first number, and ending when the count is less than asecond number; and means for providing said alarm signal in response tothe count of said clutter gate counter means.

27. The device of claim 26 wherein said clutter gate counter meansincludes a clutter gate circuit for providing a clutter gate signalduring said clutter gate interval; a ring counter enable by said cluttergate signal for providing an output signal indicative of a group of apredetermined number of range bins having occurred during said cluttergate interval; and a clutter gate counter circuit for counting thenumber of said group of range bins occuring each range sweep period; andsaid alarm means includes an alarm logic circuit adapted to provide analarm output signal when the count of said clutter gate counter circuitexceed a selected value.

1. A moving target signal processor for use with a scanning type energytransmission and reception system, said processor comprising: aplurality of clutter canceller units each adapted for processingsuccessive range sweeps of received signals and having differing cluttercancellation characteristics which are a function of the number of rangesWeeps of received signals from the same scan location processedthereby; and means for sensing the clutter energy content in saidreceived signals and in the output signals of said clutter cancellerunits, and for commanding additional transmissions at the same scanlocation, if during the current range sweep period the clutter energycontent of said received signals and the output signals from saidclutter canceller units is in excess of predetermined amounts.
 2. Theprocessor of claim 1 wherein said means for sensing clutter energy andfor commanding additional transmissions includes: clutter detectionmeans for providing alarm signals during each range sweep period, whichare indicative of clutter energy content in excess of said predeterminedamounts in said received signals and in the output signals of saidclutter canceller units, respectively, and logic control meansresponsive to said alarm signals, for providing control signals forcommanding additional transmissions at the same scan location, if duringthe current range sweep period the clutter energy content of saidreceived signals and the output signals from said clutter cancellerunits is in excess of said predetermined amounts.
 3. The processor ofclaim 2 wherein said clutter detection means includes means forproviding an alarm signal associated with any given clutter cancellerunit only during selected range sweep periods in which effective outputsignals of reduced clutter content can be provided by said any givenclutter canceller unit, said selected range sweep periods beingpredetermined as a function of the characteristics of said given cluttercanceller unit.
 4. The processor of claim 1 further comprising a signaloutput terminal; and selection means for determining if said receivedsignals or one of said output signals from said clutter canceller unitshas less than said predetermined amounts of clutter energy, and forapplying said signals with less than said predetermined amount ofclutter energy to said output terminal.
 5. The processor of claim 3further comprising a signal output terminal; and selection means fordetermining if said received signals, or one of said output signals fromsaid clutter canceller units during the respective selected range sweepperiods associated with each of the clutter canceller units, has lesssaid predetermined amounts of clutter energy, and for applying saidsignal with less than said predetermined amount of clutter energy tosaid output terminal.
 6. The processor of claim 1 further including adoppler processor unit; and means for commanding a pulse doppler burstof successive transmissions, if the clutter energy content of saidreceived signals and the output signals from said clutter cancellerunits is in excess of said predetermined amounts during a predeterminednumber of range sweep periods at the same scan location.
 7. Theprocessor of claim 5 further comprising a doppler processor unit; andmeans for commanding a pulse doppler burst of successive transmissionsif the clutter energy content of said received signals and the outputsignals from said clutter canceller units during the respective selectedrange sweep periods associated with each of the clutter canceller units,is in excess of said predetermined amounts, during a predeterminednumber of range sweep periods at the same scan location.
 8. Theprocessor of claim 7 including means for sensing the completion of thepulse doppler burst and for then coupling the output of said dopplerprocessor to said output terminal.
 9. The processor of claim 2 adaptedfor use with a pulse compression type scanned energy transmission andreception system; and wherein said clutter detection means includescounter means for statically determining during each range sweep periodif clutter energy content in excess of predetermined amounts is presentin the uncompressed received signals and in the uncompressed outputsignals of said canceller units.
 10. The processor of claim 9 wheReinsaid counter means includes a plurality of processing channels, each ofwhich is coupled to receive said received signals or the output signalsfrom one of said clutter canceller units, and including: a thresholdcircuit for providing an output signal during range bin intervals inwhich the signals applied to said channel exceeds a threshold level; anup-down counter mechanized to count up towards a preselected maximumcount during each range bin interval in which an output signal isprovided by said threshold circuit, and for counting down towards apreselected minimum count during each range bin interval in which anoutput signal is not provided by said threshold circuit; and alarm meansresponsive to the count of said up-down counter for providing an alarmsignal indicative of a clutter content in the applied signals in excessof said predetermined amount.
 11. The processor of claim 10 furthercomprising a signal output terminal; and selection means for determiningif said received signal or one of said output signals from said cluttercanceller units has less than said predetermined amounts of clutterenergy, and for applying said signal with less than said predeterminedamount of clutter energy to said output terminal.
 12. The processor ofclaim 11 further comprising a pulse compressor unit coupled to saidsignal output terminal for processing said signal having less than saidpredetermined amount of clutter energy content, so as to provide signalscompressed in the range dimension.
 13. The processor of claim 10 whereinsaid alarm means includes clutter gate counter means for counting rangebin intervals, during a clutter gate interval starting when the count ofsaid up-down counter is greater than a first number, and ending when thecount is less than a second number; and means for providing said alarmsignal in response to the count of said clutter gate counter means. 14.The processor of claim 13 wherein said clutter gate counter meansincludes a clutter gate circuit for providing a clutter gate signalduring said clutter gate interval; a ring counter enable by said cluttergate signal for providing an output signal indicative of a group of apredetermined number of range bins having occurred during said cluttergate interval; and a clutter gate counter circuit for counting thenumber of said group of range bins occurring each range sweep period;and said alarm means includes an alarm logic circuit adapted to providean alarm output signal when the count of said clutter gate countercircuit exceed a selected value.
 15. The processor of claim 14 whereinsaid alarm means includes means for inhibiting the generation of saidalarm output signal except during selected ones of the range sweeps atthe same scan location.
 16. A moving target signal processor for usewith a scanning, pulse compression type energy transmission andreception system, said processor comprising: a plurality of cluttercanceller units each adapted for processing range sweeps of uncompressedreceived signals; clutter detection means for statically determiningduring each range sweep if clutter energy content in excess ofpredetermined amounts is present in said uncompressed received signalsand in the output signals of said clutter canceller units, respectively;and logic control means coupled to said clutter detection means forcommanding an additional transmission at the same scan location ifduring the current range sweep the clutter energy content of saidreceived signals and the output signals from said clutter cancellerunits is in excess of said predetermined amounts.
 17. The processor ofclaim 16 further comprising a signal output terminal; and selectionmeans coupled to said clutter detection means for determining if saidreceived signals or if one of said output signals from said cluttercanceller units has less than said predetermined amount of clutterenergy, and for applying said signals with less than said predeterminedamount of clutter energy to said output terminal.
 18. The processor ofclaim 17 further comprising a pulse compressor unit coupled to saidsignal output terminal for processing said signals having less than saidpredetermined amounts of clutter energy, so as to provide timecompressed output signals having less than said predetermined amount ofclutter content.
 19. The processor of claim 17 further comprising adoppler processor unit; and said logic control means includes means forproviding a doppler command signal for commanding a pulse doppler burstof successive transmissions if the clutter energy content of saidreceived signals and the output signals from said clutter cancellerunits is in excess of said predetermined amounts during a predeterminednumber of range sweep periods at the same scan location.
 20. Theprocessor of claim 19 wherein said selection means includes means forsensing the completion of the pulse doppler burst and for then couplingthe output of said doppler processor to said output terminal.
 21. Theprocessor of claim 16 wherein said clutter detection means includescounter means for statically determining during each range sweep periodif clutter energy content in excess of predetermined amounts is presentin the uncompressed received signals and in the uncompressed outputsignals of said canceller units.
 22. The processor of claim 21 whereinsaid counter means includes a plurality of processing channels, each ofwhich is coupled to receive said received signals or the output signalsfrom one of said clutter canceller units, and including: a thresholdcircuit for providing an output signal during range bin intervals inwhich the signals applied to said channel exceeds a threshold level; anup-down counter mechanized to count up towards a preselected maximumcount during each range bin interval in which an output signal isprovided by said threshold circuit, and for counting down towards apreselected minimum count during each range bin interval in which anoutput signal is not provided by said threshold circuit; and alarm meansresponsive to the count of said up-down counter for providing an alarmsignal indicative of a clutter content in the applied signals in excessof said predetermined amount.
 23. The processor of claim 22 wherein saidalarm means includes clutter gate counter means for counting range binintervals during a clutter gate interval starting when the count of saidup-down counter is greater than a first number, and ending when thecount is less than a second number; and means for providing said alarmsignal in response to the count of said clutter gate counter means. 24.The processor of claim 23 wherein said clutter gate counter meansincludes a clutter gate circuit for providing a clutter gate signalduring said clutter gate interval; a ring counter enabled by saidclutter gate signal for providing an output signal indicative of a groupof a predetermined number of range bins having occurred during saidclutter gate interval; and a clutter gate counter circuit for countingthe number of said group of range bins occuring each range sweep period;and said alarm means includes an alarm logic circuit adapted to providean alarm output signal when the count of said clutter gate countercircuit exceed a selected value.
 25. A device for detecting clutterenergy in the received signals from a pulse compression type energytransmission and reception system, said device comprising: a thresholdcircuit for providing an output signal during range bins intervals inwhich the received signals exceeds a threshold level; an up-down countermechanized to count up towards a preselected maximum count during eachrange bin interval in which an output signal is provided by saidthreshold circuit, and for counting down towards a preselected minimumcount during each range bin interval in which an output signal is notprovided by said threshold circuit; and alarm means responsive to thecount of said up-down counter for providing an alarm signaL indicativeof a clutter content in the applied signal in excess of a predeterminedamount.
 26. The device of claim 25 wherein said alarm means includesclutter gate counter means for counting range bin intervals, during aclutter gate time interval starting when the count of said up-downcounter is greater than a first number, and ending when the count isless than a second number; and means for providing said alarm signal inresponse to the count of said clutter gate counter means.
 27. The deviceof claim 26 wherein said clutter gate counter means includes a cluttergate circuit for providing a clutter gate signal during said cluttergate interval; a ring counter enable by said clutter gate signal forproviding an output signal indicative of a group of a predeterminednumber of range bins having occurred during said clutter gate interval;and a clutter gate counter circuit for counting the number of said groupof range bins occuring each range sweep period; and said alarm meansincludes an alarm logic circuit adapted to provide an alarm outputsignal when the count of said clutter gate counter circuit exceed aselected value.